1. Field of the Invention
The invention relates generally to circuitry design, more specifically, the invention relates to modeling of an anti-resonance circuit for a central processing unit.
2. Background Art
As today's computer systems operate at frequencies exceeding 1 GHz, the demands on internal power supplies also increase. For instance, as the technology is scaled smaller and faster, the power supply voltage must decrease. However, as the internal clock rates rise and more functions are integrated into microprocessors and application specific integrated circuits (ASICs), the total power consumed must increase. These demands require the internal power supply to respond quickly and reliably without significant overshoot, undershoot, or ringing of the supplied voltage.
Obviously, the design of the power system is critical to meeting these stringent requirements. A critical part of the design process is the modeling of the system. Typically, a model is used to simulate the system's performance so that design decisions can be made based on its results. The key questions in developing a model are: (1) the level of complexity it will entail; and (2) the degree of accuracy it will provide with its results. As a general rule, a more complex model has greater accuracy in its results. However, a complex model may take several days of operation just to simulate a few micro-seconds of system time.
FIG. 1 shows a prior art depiction of a central processing unit (CPU) power distribution system 10 with power system components that must be simulated by such a model. The main circuit board 12 itself is the central platform with the system power supply board 14 and system ground board 16 layered underneath. Attached to the surface of the board 10 is the circuit package 18 that holds the central processing unit 20 or “chip”. Also shown are various components of the power system including: high-capacity ceramic capacitors 22; an air-core inductor 24; a regulating integrated circuit 26; switching transistors 28; a mid-capacity tantalum capacitor 30; and low-capacity electrolytic capacitors 32.
Of these components, the model of the chip 20 is the most difficult to develop. As the chips have achieved greater and greater speeds, these circuits have become more and more sensitive to the effects of parasitic inductance. The parasitic inductance can come from such sources as bond wires, IC package leads, and external supply lines that provide operating power. The problem with such characteristics is that they form a very high supply line impedance at a resonance frequency. This may lead to circuit oscillation 34 as shown in FIG. 2. In order to avoid such undesirable effects on circuit operation, the parasitic inductance must be suitably controlled in order to achieve a substantially non-oscillating waveform 36 as shown in FIG. 3.
Prior art methods of controlling parasitic inductance include connecting an external capacitor between the supply leads. This connection creates a passive bypass that decreases the supply line oscillation due to external inductances. However, it does not significantly reduce the oscillation caused by internal inductances. Another prior art method includes connecting an on-chip capacitor between the internal supply leads. The capacitor acts as a bypass in the same manner as an external capacitor. However, in order to be effective, the internal capacitor must be very large. This has the drawback of occupying a significant portion of the chip area. Consequently, this method is generally undesirable when minimization of the die area is of great importance.
Another prior art approach involves increasing the amount of charge stored or delivered to a given amount by actively increasing the voltage variation across their terminals with added on-chip de-coupling capacitance. FIG. 4 shows a schematic of this technique with resistance losses. In this method, fully charged capacitors 38 and 40 of equal value are stacked in series 42 across the on-chip Vdd/Vss grid. The capacitors serve as a voltage multiplier for the Vdd/Vss grid. The depleted voltage in each capacitor is Vdd/n, where n is the number of capacitor stacks. Conversely, the stacked capacitors will store charge from the Vdd/Vss grid until the terminals across the capacitors are fully at Vdd.
A capacitance amplification factor (G) represents the charge supplied to the grid by the switched capacitors normalized to the charge furnished by regular de-coupled capacitors given the same supply voltage variation. The amplification can be expressed as G=(k+n−1)/(k*n2), where n is the number of stacks and k is the voltage regulation tolerance. With each capacitor having a value (Cd), the equivalent unstacked capacitance of Cd*n is reduced to Cd/n upon stacking with a total stack voltage of Vdd*n.
FIG. 5a shows a schematic 44 of an implementation of the method of FIG. 4. The circuit shows mutually exclusive CMOS switches that configure the capacitors (C2) 46 and (C1) 48 to either be in the charging phase (shunt across Vdd/Vss) or in the discharging phase (in series with Vdd/Vss). The circuit has two sections: the Vave (average voltage) tracking loop 50 and the Vinst (instant voltage) monitor and charge pump loop 52. The monitor and charge pump loop 52 is physically located on the chip. The switches are driven by two complementary drivers (comparators) 54 and 56. These drivers each provide two outputs with enough voltage offset to ensure minimal leakage through both charge and discharge switches during switching activity.
Instantaneous voltage supply variation (Vinst) is monitored by coupling the Vdd and Vss onto the comparator 56 input that is dynamically biased about a reference voltage (Vave). Vave is a high-pass filtered version of the local ((Vdd−Vss)/2. Its low frequency cutoff clears the low end resonance range, but it also rejects the tracking of low-frequency disturbances that are not due to resonance. The coupled Vinst feed the main negative feedback loop as charge is pumped in and out of the switched capacitors 46 and 48 coupled to the Vdd/Vss grid in an attempt to defeat the voltage variations. The compensated high frequency cutoff ensures stable loop response while also clearing the high end of the resonance range.
FIG. 5b shows the operation of the circuit shown in FIG. 5a. Specifically, the graph shows: a steady state when Vinst=Vave; a discharging phase when Vinst<Vave; and a charging phase when Vinst>Vave. The high frequency and low frequency cutoffs are also shown for their respective phases.
The net result is that this analog circuit described herein senses when the supply is collapsing and then it acts by charging/discharging to ensure stability in the power supply. However, a model of such a package/chip anti-resonance circuit is needed that provides accurate results in an acceptable amount of simulation time.